1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to a simultaneous multi-threaded (SMT) processor. The present invention also relates to supervisory processor control logic and external supervisory and test ports.
2. Description of the Related Art
Present-day high-speed processors include the capability of simultaneous execution of instructions, speculative execution and loading of instructions and simultaneous operation of various resources within a processor. In particular, it has been found desirable to manage execution of one or more threads within a processor, so that more than one execution thread may use the processor and so that resources more effectively than they are typically used by a single thread.
Present-day computer systems also typically include secondary service processors that are used to initialize and monitor the primary processors within a computer system. Such service processors typically have very powerful control capability with respect to the primary processors to which they are connected of complete control of internal caches, processor core(s) and other logical units within a processor and are typically connected via a test port such as a Joint Test Action Group (JTAG) test port. Although JTAG ports were first developed for boundary-scan manufacturing test applications, use of the JTAG port for external supervisory control of a primary processor by a service processor has been implemented for convenience and simplicity of interconnect.
Simultaneous multi-threaded (SMT) processors provide very efficient use of processor resources, as multiple threads may simultaneously use processor resources. Multiple threads are concurrently executed in an SMT processor so that multiple processor execution units, such as floating point units, fixed point instruction units, load/store units and others can be performing tasks for one (or more depending on the execution units' capabilities) of multiple threads simultaneously.
However, synchronization between thread states that may be changing rapidly within an SMT processor and supervisory commands issued via a test port arrive at processor cores relatively slowly. Therefore, certain service processor controls cannot be readily issued if the execution states of one or more threads may change prior to arrival of the command, as the controls may “crash” the primary processor, causing corruption of data and system errors.
It is therefore desirable to provide a method and apparatus that provide a mechanism for issuing thread-execution-state-sensitive supervisory commands to an SMT processor.